The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method and device for manufacturing a metal inter-connect structure having a metal insulator metal capacitor structure for mixed signal devices. Merely by way of example, the invention has been applied to a copper metal damascene structure such as a dual damascene structure for mixed signal processing devices. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to microprocessor devices, memory devices, application specific integrated circuit devices, as well as various other interconnect structures.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each procell used in IC fabrication has a limit. That is to say, a given process typically only words down to a certain feature size, and then either the process or the device layout needs to be changed. An example of such a limit is the ability to form interchanging metal and dielectric layers, where the metal layers do not interact with each other in the form of noise.
As merely an example, parallel plate capacitor structures have been used. Such structures have been described in R. Liu et al., titled “Single Mask Metal-Insulator-Metal (MIM) Capacitor with Copper Damascene Metallization for Sub-0.18 μm Mixed Mode Signal and System-On-a-Chip (SoC) Applications” Proc. 2000 IITC, pp. 111–113 (2000). R. Liu et al. generally describes the parallel plate capacitor design. Parallel plate capacitor design often uses two fairly large electrodes and a capacitor dielectric sandwiched in between. Numerous limitations exist. For example, such design often takes a lot of area to provide a desirable capacitance for mixed mode integrated circuit devices. These and other limitations are described throughout the present specification and more particularly below.
From the above, it is seen that an improved technique for processing semiconductor devices is desired.